The disclosure herein relates generally to designing and fabricating a semiconductor quasi-vertical gated NPN-PNP electrostatic discharge (ESD) protection device.
Electrostatic discharge (ESD) is a continuing problem in the design, manufacture and utilization of semiconductor devices. A major source of ESD exposure to ICs is from the human body (described by the “Human Body Model”, HBM). In this situation, a packaged IC acquires a charge when it is held by a human who is electrostatically charged (e.g., from walking across carpeting). A charge of about 0.6 μC can be induced on a body capacitance of 150 pF, for example, leading to electrostatic potentials of 4 kV or greater and discharging peak currents of several amperes to the IC for about 100 ns, for example. A second source of ESD is from metallic objects (described by the “Machine model”, MM), which is characterized by a greater capacitance, lower internal resistance and transients that have significantly higher rise times and current levels than the HBM ESD source. A third source is described by the “charged device model” (CDM), in which the IC itself becomes charged and discharges to ground in rise times less than 500 ps in the opposite direction than the HBM and MM ESD sources. Furthermore, different types of electrical overstresses during circuit operation are defined in standards dedicated to specific applications like automotive systems.
During ESD events, current is typically discharged between one or more pins or pads exposed to the outside of an IC chip. Such ESD current flows from the pad to ground through vulnerable circuitry in the IC, which may not be designed to carry such currents. Many ESD protection techniques have been employed to reduce or mitigate the adverse effects of ESD events in integrated circuit devices. Many conventional ESD protection schemes for ICs employ peripheral circuits to carry the ESD currents from the pin or pad of the device to ground by providing a low impedance path thereto. In this way, the ESD currents flow through the protection circuitry, rather than through the more susceptible circuits in the chip. In some cases it is also possible to make a device of weak intrinsic ESD robustness self-protecting by some device design modifications which do not impact significantly device function under normal operation.
ESD protection devices, circuits or self protecting elements are typically connected to I/O and other pins or pads on the IC, wherein the pads further provide the normal circuit connections for which the IC was designed.
In the last 20 years, the increasing need for advanced Smart Power circuits, integrating power drivers, high density logic control units, high precision analog circuits and various memories in single chip solutions to be used in increasingly harsh environments has made the development of robust and compact ESD protection devices highly desirable.